Register defs
(DWORD offset from daughtercard base, 0x80380000 for C671x, 0xFE0000 for C33)

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	ADC_DATA : read only
		Addr (DWORDS)	: 0x0000-0x00FF (0x000-0x3FC)
		Size (DWORDS)	: 64
		ADC_DATA bits	:
			0..15	: ADC data
			16..31	: N/A

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	DAC_DATA : 
		Addr (DWORDS)	: 0x0100-0x01FF (0x400-0x7FC)
		Size (DWORDS)	: 64 (only 16 used)
		DAC_DATA bits	:
			0..15	: DAC data
			16..31	: N/A

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	FPGA_VERSION : read only
		Addr (DWORDS)	: 0x0200 (0x800)
		Size (DWORDS)	: 1
		FPGA_VERSION bits :
			0..29	: FPGA version number
			31..30	: ADC Circuit
				00 : n/a
				01 : LTC1864
				10 : ADS8325
				11 : n/a


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	TIMING_CSR : read/write
		Addr (DWORDS)	: 0x0201 (0x804)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0	: EXT_DDS_RST
					0: on (default)
					1: reset/clr
			1	: EXTCLK_EN
					0: input (default)
					1: output, ADC sample clock source
			2	: SAMPLE_MODE
					0: traditional muxed (default)
					1: pseudo simultaneous
			3..5	: DDS0_CLK_SRC
					000: S/W or free run (default)
					001: EC0 Triggered, DDS0 is synchronously enabled after
					the EC0 reaches treshold.
					010: EC1 Triggered, DDS0 is synchronously enabled after
					the EC1 reaches treshold.
					011: EC2 Triggered, DDS0 is synchronously enabled after
					the EC2 reaches treshold.
					100: EC3 Triggered, DDS0 is synchronously enabled after
					the EC3 reaches treshold.

			6..8	: DDS1_CLK_SRC
					000: S/W or free run (default)
					001: EC0 Triggered, DDS1 is synchronously enabled after
					the EC0 reaches treshold.
					010: EC1 Triggered, DDS1 is synchronously enabled after
					the EC1 reaches treshold.
					011: EC2 Triggered, DDS1 is synchronously enabled after
					the EC2 reaches treshold.
					100: EC3 Triggered, DDS1 is synchronously enabled after
					the EC3 reaches treshold.

			9..12	: SampleClk Source
					0000 (0x0) : internal DDS0 (default)
					0001 (0x1) : internal DDS1
					0010 (0x2) : external DDS
					0011 (0x3) : external sample clock
					0100 (0x4) : EC0
					0101 (0x5) : EC1
					0110 (0x6) : EC2
					0111 (0x7) : EC3

					1000 (0x8) : GPIO0
					1001 (0x9) : GPIO1
					1010 (0xA) : GPIO2
					1011 (0xB) : GPIO3

			13..31	: N/A

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	EC0_CSR : read/write
		Addr (DWORDS)	: 0x0202 (0x808)
		Size (DWORDS)	: 1
		Bit Definitions	:

			0	: EC0_RESET; r/w
					0: on, free run (default)
					1: reset/clr, clears EC value irrespective of state/enable line.
			1	: EC0_ENABLE; r/w
					0: enable, free run, EC counter is actively counting (default).
					1: disable, EC counter is detained, but NOT cleared/reset.
			2	: EC0_WRAP_MODE; r/w
					0: Free running, automatically wraps after reaching its threshold/limit
					(as long as there is a tick source), (default).
					1: Counts until reaches the threshhold, then stops and retains/latches
					value until RESET/CLR is asserted.
			3	: EC0_POLARITY; r/w
					0: Positive edge tick source (default)
					1: Negative edge tick source

			4..6	: N/A

			7	: EC0_OUT; read only. This signal may be used as a synchronous source to trigger other devices.
					0: LO during count
					1: HI when threshhold/limit reached.
			8..12	: EC0_TickClock Source; r/w
					00000 (0x0) : internal DDS0
					00001 (0x1) : internal DDS1 (default)
					00010 (0x2) : external DDS
					00011 (0x3) : external sample clock
					00100 (0x4) : PWM0
					00101 (0x5) : PWM1
					00110 (0x6) : PWM2
					00111 (0x7) : PWM3
					01000 (0x8) : EC1
					01001 (0x9) : EC2
					01010 (0xA) : EC3
					01011 (0xB) : DSP Ref Clk (37.5Mhz)
					01100 (0xC) : S/W (bit 31)

					10000 (0x10) : QE0
					10001 (0x11) : QE1

			13..30	: N/A
			31	: S/W Pulse. When accessed, a software trigger is created, useful in creating a software controlled trigger for EC. In order for a S/W trigger to occur, a LO-HI or HI-LO transition sequence must occur for the edge to recognized.
					0: LO level on S/W trigger.
					1: HI level on S/W trigger.

	EC1_CSR : read/write
		Addr (DWORDS)	: 0x0203 (0x80C)
			8..12	: EC0_TickClock Source; r/w
					00000 : internal DDS0
					00001 : internal DDS1 (default)
					00010 : external DDS
					00011 : external sample clock
					00100 : PWM0
					00101 : PWM1
					00110 : PWM2
					00111 : PWM3
					01000 : EC0
					01001 : EC2
					01010 : EC3
					01011 : DSP Ref Clk (37.5Mhz)
					01100 : S/W (bit 31)

					10000 : QE0
					10001 : QE1

	EC2_CSR : read/write
		Addr (DWORDS)	: 0x0204 (0x810)
			8..12	: EC0_TickClock Source; r/w
					00000 : internal DDS0
					00001 : internal DDS1 (default)
					00010 : external DDS
					00011 : external sample clock
					00100 : PWM0
					00101 : PWM1
					00110 : PWM2
					00111 : PWM3
					01000 : EC0
					01001 : EC1
					01010 : EC3
					01011 : DSP Ref Clk (37.5Mhz)
					01100 : S/W (bit 31)

					10000 : QE0
					10001 : QE1


	EC3_CSR : read/write
		Addr (DWORDS)	: 0x0205 (0x814)
			8..12	: EC0_TickClock Source; r/w
					00000 : internal DDS0
					00001 : internal DDS1 (default)
					00010 : external DDS
					00011 : external sample clock
					00100 : PWM0
					00101 : PWM1
					00110 : PWM2
					00111 : PWM3
					01000 : EC0
					01001 : EC1
					01010 : EC2
					01011 : DSP Ref Clk (37.5Mhz)
					01100 : S/W (bit 31)

					10000 : QE0
					10001 : QE1


	EC0_CNT_LIMIT: SampleClock_Counter_Limit or threshold, read/write. When a value of '0' is entered, EC is disabled; when a value of '1' is entered, the EC_OUT will assert after the first 'tick' and so on.
		Addr (DWORDS)	: 0x0206 (0x818)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0..15	: SampleClock_Counter_Limit; 0 value increments by single count or '1'
			16..31	: N/A

	EC1_CNT_LIMIT: SampleClock_Counter_Limit or threshold, read/write. When a value of '0' is entered, EC is disabled; when a value of '1' is entered, the EC_OUT will assert after the first 'tick' and so on.
		Addr (DWORDS)	: 0x0207 (0x81C)
	EC2_CNT_LIMIT: SampleClock_Counter_Limit or threshold, read/write. When a value of '0' is entered, EC is disabled; when a value of '1' is entered, the EC_OUT will assert after the first 'tick' and so on.
		Addr (DWORDS)	: 0x0208 (0x820)
	EC3_CNT_LIMIT: SampleClock_Counter_Limit or threshold, read/write. When a value of '0' is entered, EC is disabled; when a value of '1' is entered, the EC_OUT will assert after the first 'tick' and so on.
		Addr (DWORDS)	: 0x0209 (0x824)


	EC0_CNT_VALUE: Internal Counter value, read only.
		Addr (DWORDS)	: 0x020A (0x828)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0..15	: SampleClock_Counter_Limit
			16..31	: N/A
	EC1_CNT_VALUE: Internal Counter value, read only.
		Addr (DWORDS)	: 0x020B (0x82C)
	EC2_CNT_VALUE: Internal Counter value, read only.
		Addr (DWORDS)	: 0x020C (0x830)
	EC3_CNT_VALUE: Internal Counter value, read only.
		Addr (DWORDS)	: 0x020D (0x834)


Triggerable Event Counter (EC) Notes:

1) The EC will have an internal 'direction' input:
	dir: UP/DN for QE inputs.
	dir: always 'UP' for PWM inputs.
2) Example for testing: If the 'tick count threshold' is set to a '1', the EC input tick source can be nothing more than a single transition in order to trigger its output, thus creating the equivalent of an 'event marker'.

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	INT_DDS0_PADATA : read/write
		Addr (DWORDS)	: 0x0210 (0x840)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0..26	: PA0 data
			27..31	: N/A

	INT_DDS1_PADATA : read/write
		Addr (DWORDS)	: 0x0211 (0x844)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0..26	: PA1 data
			27..31	: N/A

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	EXT_DDS_PADATA : write only. The ADS9850 requires 5 separate write cycles.
		Addr (DWORDS)	: 0x0218 (0x860)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0..7	: DDS data
			8..31	: N/A

	EXT_DDS_LOAD : write only
		Addr (DWORDS)	: 0x0219 (0x864)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0..31	: N/A

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	DAC_CSR : 
		Addr (DWORDS)	: 0x0220 (0x880)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0	: DACCLK value when in manual mode
			1	: DACCLK_Mode
					0 = 1/2 of daughter clock (default)
					1 = manual mode

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	DIO_CSR : r/w
		Addr (DWORDS)	: 0x0224 (0x890)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0	: DIODIR_LW
					0: LWord[15:0] Input
					1: LWord[15:0] Output
			1	: DIODIR_HW
					0: HWord[31:16] Input
					1: HWord[31:16] Output
			28	: DIO Mode
					0: Basic
					1: Adv
			29	: DIO Setting
					0: Master
					1: Slave
			30	: DIO Adv. Mode Write
					0:
					1:
			31 	: DIO Adv. Mode Read
					0:
					1:


	DIO_PORT32 : r/w
		Addr (DWORDS)	: 0x0225 (0x894)
		Size (DWORDS)	: 1
		Bit Definitions	:
			0..31	: digital IO values

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	GPIO_CSR : r/w
		Addr (DWORDS)	: 0x0228 (0x8A0)
		Size (DWORDS)	: 1
		GPIO_CSR bits	:
			0,1	: GPIO[0:1]_SEL
					00 (0): AUX_DIO[0:1]
					01 (1): PULSEIO[0:1]
					10 (2): QE0
					11 (3): reserved
			2,3	: GPIO[2:3]_SEL
					00 (0): AUX_DIO[2:3]
					01 (1): PULSE[2:3]
					10 (2): QE1
					11 (3): reserved
			4..5	: FREE_COUNTER_SRC
					00 (0): DSP Ref Clk (37.5Mhz)
					01 : n/a
					10 : n/a
					11 : n/a
			6..31	: N/A


	GPIO_COUNTER32 : read only
		Addr (DWORDS)	: 0x0229 (0x8A4)
		Size (DWORDS)	: 1
		GPIO_COUNTER32_0 bits:
			0..31	: free running 32 bit counter

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	AUX_DIO_CSR : r/w
		Addr (DWORDS)	: 0x022C (0x8B0)
		Size (DWORDS)	: 1
		DIO_CSR bits	:
			0	: AUX_DIO_DIR
				0 = input to FPGA (default)
				1 = output from FPGA

			1..31	: N/A

	AUX_DIO_PORT: r/w
		Addr (DWORDS)	: 0x022D (0x8B4)
		Size (DWORDS)	: 1
		AUX_DIO_0 bits :
			0..3	: digital IO values
			4..31	: N/A

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	PULSEIO_CSR : 
		Addr (DWORDS)	: 0x0230 (0x8C0)
		Size (DWORDS)	: 1
		PWM_CSR bits	:
			0	: PULSEIN0_RESET; r/w
					0: on, free run (default)
					1: reset/clr, clears PULSEIN0 registers.
			1	: PWMOUT0_RESET; r/w
					0: on, free run (default)
					1: reset/clr, clears PWMOUT0 counter/value.
			2	: PULSEIN1_RESET; r/w
					0: on, free run (default)
					1: reset/clr, clears PULSEIN1 registers.
			3	: PWMOUT1_RESET; r/w
					0: on, free run (default)
					1: reset/clr, clears PWMOUT1 counter/value.

			4..31	: N/A

	PULSEIN0_CSR0 : read only
		Addr (DWORDS)	: 0x0231 (0x8C4)
		Size (DWORDS)	: 1
		PULSEIN0_CSR0 bits:
			0..31	: COUNTER32 value indicating the time when the first of three edges occurred.
	PULSEIN0_CSR1 : read only
		Addr (DWORDS)	: 0x0232 (0x8C8)
		PULSEIN0_CSR1 bits:
			0..31	: COUNTER32 value indicating the time when the second of three edges occurred.
	PULSEIN0_CSR2 : read only
		Addr (DWORDS)	: 0x0233 (0x8CC)
		PULSEIN0_CSR2 bits:
			0..31	: COUNTER32 value indicating the time when the last of three edges occurred.
	PULSEIN0_CSR3 : read/write. When written, all four PULSEIN0_CSRs are registered.
				When read, bit 0 serves as an indicator to describe the order of the incoming pulses.
		Addr (DWORDS)	: 0x0234(0x8D0)
		Size (DWORDS)	: 1
		PULSEIN0_CSR3 bits:
			0	: Pointer/indicator
					0: Rising/Falling/Rising
					1: Falling/Rising/Falling
			1..31	: n/a

	PWMOUT0_Rising : 
		Addr (DWORDS)	: 0x0235 (0x8D4)
	PWMOUT0_Falling : 
		Addr (DWORDS)	: 0x0236 (0x8D8)

	PULSEIN1_CSR0 : read only
		Addr (DWORDS)	: 0x0237 (0x8DC)
		Size (DWORDS)	: 1
		PWMIN0_CSR0 bits:
			0..31	: When PWM is Input, COUNTER32 value when rising edge occurred
				  When PWM is Output, tick counts for positive edge to occur.
	PULSEIN1_CSR1 : read only
		Addr (DWORDS)	: 0x0238 (0x8E0)
	PWMIN1_CSR2 : read only
		Addr (DWORDS)	: 0x0239 (0x8E4)
	PWMIN1_CSR3 : read/write. When written, the four PWM CSRs are registered.
				When read, bit 0 serves as a pointer to describe the order of the incoming pulses.
		Addr (DWORDS)	: 0x023A(0x8E8)
		Size (DWORDS)	: 1
		PWMIN0_CSR3 bits:
			0	: Pointer/indicator
					0: Rising/Falling/Rising
					1: Falling/Rising/Falling
			1..31	: n/a

	PWMOUT1_Rising : 
		Addr (DWORDS)	: 0x023B (0x8EC)
	PWMOUT1_Falling : 
		Addr (DWORDS)	: 0x023C (0x8F0)

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	QE_CSR : r/w
		Addr (DWORDS)	: 0x0250 (0x940)
		Size (DWORDS)	: 1
		QE_CSR bits	:
			0..3	: QE0_WAIT_PERIOD[0:3]. A digital average or filter, an input line must retain the same value as the ratio in order to be considered a valid value.
			4..6	: QE0_CNT_MODE
					000 = x1 pulses (default)
					001 = x2 pulses
					010 = x4 pulses
					011 = N/A
					100 = Up/Dn Clk
					101 = Dir/Clk
			7	: n/a
			8..11	: QE1_WAIT_PERIOD[0:3]. A digital average or filter, an input line must retain the same value as the ratio in order to be considered a valid value.
			12..14	: QE1_CNT_MODE
					000 = x1 pulses (default)
					001 = x2 pulses
					010 = x4 pulses
					011 = N/A
					100 = Up/Dn Clk
					101 = Dir/Clk
			15..31	: n/a

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	SCAN_TABLE : 
		Addr (DWORDS)	: 0x0300 (0xC00)
		Size (DWORDS)	: 32
		SCAN_TABLE bits	:
			0..2	: MUXA[0:2]
			3	: SYNC
			4..7	: N/A
			8..9	: MUXB0[0:1]
			10..11	: MUXB1[0:1]
			12..13	: MUXB2[0:1]
			14..15	: MUXB3[0:1]
			16..17	: LOGAIN_PGA0[0:1]
			18..19	: LOGAIN_PGA1[0:1]
			20..21	: LOGAIN_PGA2[0:1]
			22..23	: LOGAIN_PGA3[0:1]
			24..25	: HIGAIN_PGA0[2:3]
			26..27	: HIGAIN_PGA1[2:3]
			28..29	: HIGAIN_PGA2[2:3]
			30..31	: HIGAIN_PGA3[2:3]

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** Debugging space **

	ADC_Count and Status : 
		Addr (DWORDS)	: 0x0400 (0x1000)
		Size (DWORDS)	: 1
		  bits		:
			0..29	: Sample Clock Counter


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