# Reading F:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do tb_generic_top_rw.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity if_dsp
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture behavioral of if_dsp
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity if_dsp
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity if_mem
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture behavioral of if_mem
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity if_mem
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity generic_top
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture structural of generic_top
# -- Loading package std_logic_1164
# -- Loading entity generic_top
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity if_mem
# -- Loading entity if_dsp
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity testbench
# Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002
# -- Loading package standard
# -- Compiling architecture testbench_arch of testbench
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading entity testbench
# -- Loading entity generic_top
# -- Compiling configuration myer_top_cfg
# -- Loading entity testbench
# -- Loading architecture testbench_arch of testbench
# vsim -L xilinxcorelib -lib work -t 1ps testbench 
# ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.# Loading F:/Modeltech_xe_starter/win32xoem/../std.standard
# Loading F:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
# Loading F:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
# Loading F:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.testbench(testbench_arch)
# Loading work.generic_top(structural)
# Loading work.if_mem(behavioral)
# Loading work.if_dsp(behavioral)
# .wave
# ** Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use.
# File in use by: Administrator  Hostname: TBIRD12G  ProcessID: 1276
# ** Warning: (vsim-WLF-5001) Could not open log file vsim.wlf.  Using E:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\wlft6.wlf instead.
# .structure
# .signals
# ** Failure: Simulation done.
#    Time: 1440 ns  Iteration: 0  Instance: /testbench
# Break at tb_generic_top_rw.vhd line 188
# Simulation Breakpoint: Break at tb_generic_top_rw.vhd line 188
# MACRO ./tb_generic_top_rw.fdo PAUSED at line 19
destroy .wave
