SI-MPC-6713DSP User Guide
8/15/10
========================================================================================
System Configuration
----------------------------------------------------------------------------------------
-------------------------------------------------
MPC 8313 Agent Mode Mapping As seen from a Host PC.
-------------------------------------------------

BADDR0:
	Content: MPC Opregs (referred by the MPC documentation as IMMR or Internal Memory Mapped Regs)
	Endianness: Big Endian access.
	Size: 1MB

BADDR1:
	Content: FPGA/DSP Regs
	Endianness: Big Endian access at MPC-LBC (LCS1) Physical Base Address 0xFF00,0000, Little Endian access (byte swapped internally) at MPC-LBC (LCS1) Physical Base Address FF10,0000.
	Size: 1MB (FIFO=128B+Comm Reg=128B+CSR=64B+HPI=16B+IO=256kB, 1MB for either Endianness)

BADDR2:
	Content: MPC Resources (DDR2, NAND Flash, etc.)
	Endianness: Big Endian access
	Size: 8MB (Variable or sliding window into MPC resources)

==============================================================================================================================================
| PCI BADDRn | Range | Endianness| MPC Physical Base Address | Resource             | Host BADDRn+Offset | DSP CEn | DSP Base Address        |
|            |       |           | (Host or Agent Mode)      |                      | (Byte Boundary)    |         | (Byte Boundary)         |
==============================================================================================================================================
| 0          | 1MB   | Big       | 0xE000,0000-0xE00F,FFFF   | MPC Internal Memory  |                    | n/a     | n/a                     |
|            |       |           |                           | Mapped Regs (IMMR)   |                    |         |                         |
-------------|-------|-----------|---------------------------|----------------------|--------------------|---------|-------------------------|
| 1          | 1MB   | Little    | 0xFF10,0000-0xFF1F,FFFF   | MPC external LCS1    | 0x0-0xF,FFFF       | 0       | 0x8020,0000-0x803B,FFFF |
|            |       | (default) |                           | configured as UPMa   |                    |         | (1792kx8)               |
|            |       |-----------|---------------------------| to access DSP/FPGA   |                    |         |                         |
|            |       | Big       | 0xFF00,0000-0xFF0F,FFFF   |                      |                    |         |                         |
-------------|-------|-----------|---------------------------|----------------------|--------------------|---------|-------------------------|
| 2          | 8MB   | Big       | ??                        | MPC external DDR2    | 0x0-0x7F,FFFF      | n/a     | n/a                     |
|            |       |           | Variable/sliding window   | (default at powerup) |                    |         |                         |
|            |       |           |---------------------------|----------------------|--------------------|         |                         |
|            |       |           | 0xE280,0000-0xE280,0FFF   | MPC external LCS0    |                    |         |                         |
|            |       |           |                           | configured as FCM    |                    |         |                         |
|            |       |           |                           | to access Flash      |                    |         |                         |
-------------|-------|-----------|---------------------------|----------------------|--------------------|---------|-------------------------|


Note: For more details, please refer to the MPC8313ERM.

-------------------------------------------------
Onboard Jumpers
-------------------------------------------------

======================================================
DIP Switch | Function       | Definition
======================================================
0:4        | M_CRS          | MPC Reset Configuration Source used to set boot mode after power on.
           |                | The lsb M_CRS4 also doubles as the HOST_AGENTn mode line:
           |                | HOST_AGENTn= 0: Agent Mode, applicable when card is plugged into a PCI slot.
           |                | HOST_AGENTn= 1: Host Mode, applicable when in stand-alone mode.
--------------------------------------------------------
5          | n/a            |
--------------------------------------------------------
7:6        | PCI104SEL[1:0] | PCI-104 Agent Mode slot number, not relevant for Host mode.
           |                |  0b00: slot 0 (default for a single PCI-104 card on stack)
           |                |  0b01: slot 1
           |                |  0b10: slot 2
           |                |  0b11: slot 3
--------------------------------------------------------


DIP[0:3] = M_RCS[0:3]
DIP3 = HOST_AGENTn (lsb M_CRS3)
DIP4 = HOSTn_AGENT
DIP5 = n/a
DIP[7:6] = PCI104SEL[1:0]

Jumper Definitions

M_RCS[0:3]= MPC Reset Configuration Source used to set boot mode after power on, with M_RCS0 acting as msb.  The lsb M_CRS4 also doubles as the HOST_AGENTn mode line described below.

M_RCS4(lsb): HOST_AGENTn mode.
	HOST_AGENTn= 0: Agent Mode, applicable when card is plugged into a PCI slot.
	HOST_AGENTn= 1: Host Mode, applicable when in stand-alone mode.

PCI104SEL[1:0]: PCI104 Agent Mode slot number, not relevant for Host mode.
	0b00: slot 0.
	0b00: slot 1.
	0b00: slot 2.
	0b00: slot 3.

-------------------------------------------------
Boot Modes
-------------------------------------------------

Boot modes are determined by M_CRS[0:3] dip switches, with M_CRS0 being the msb.

1) Boot Modes Used for Normal Operation

M_RCS[0:4] | MPC Reset Configuration Source | Operation Mode
--------------------------------------------------------
0b01001    | I2C                            | Agent-plugin
0b00010    | NAND, Small page               | Host-Standalone
0b01010    | NAND, Large page               | Host-Standalone


2) Boot Modes Used for blank I2C Update

M_RCS[0:4] | MPC Reset Configuration Source | MPC Clock Configuration             | Operation Mode
-----------------------------------------------------------------------------------------------------
0b10001    | Hard-coded option 0 | PCI=33Mhz, CSB=133Mhz, DDR=266Mhz, Core=266Mhz | Agent-plugin (default).
0b10101    | Hard-coded option 2 | PCI=33Mhz, CSB=167Mhz, DDR=333Mhz, Core=250Mhz | Agent-plugin
0b11001    | Hard-coded option 4 | PCI=33Mhz, CSB=167Mhz, DDR=333Mhz, Core=333Mhz | Agent-plugin

0b1001: Hard-coded option 1 | PCI=66Mhz, CSB=133Mhz, DDR=266Mhz, Core=333Mhz | (Not Supported).
0b1011: Hard-coded option 3 | PCI=66Mhz, CSB=133Mhz, DDR=266Mhz, Core=266Mhz | (Not Supported).

Note:
1) Other jumper positions NOT supported.
2) NAND page size legible from RCW located inside I2C.
3) For more details, please refer to the MPC8313ERM, chapter 4.3.


========================================================================================
MPC8313 Configuration
----------------------------------------------------------------------------------------
-------------------------------------------------
MPC Clocks
-------------------------------------------------

==========================================================
MPC Clock Signal | Description                | Source
============================================================
Main Clock in    | Main Clock Input           | 33.33Mhz
                 |                            |   Agent Mode: PCI bus clock routed to PCI_SYNC_IN
                 |                            |   Host Mode: SYS_CLK_IN from onboard oscillator routed to PCI_SYNC_IN
-----------------|----------------------------|------------------
VCO              | Main PLL VCO               | PCI*16 = 533Mhz
                 |                            | Internal to MPC
-----------------|----------------------------|------------------
CSB              | Coherent System Bus Clock  | MEM_MCK/2 = 133.33Mhz or
                 |                            | VCO/4 (SPMF=4) = 133.33Mhz
                 |                            | Internal to MPC
-----------------|----------------------------|------------------
eLBC or          | Local Bus Clock            | CSB/2 = 66.67Mhz
                 |                            | Internal to MPC, available
                 |                            | externally to LCLK[1:0].
                 |                            | LCLK0 feeds the FPGA,
                 |                            | LCLK1 feeds the DSP-ECLKIN.
-----------------|----------------------------|------------------
Core Clock       | e300 PPC Core Clock        | CSB*2.5 = 333.33Mhz
                 |                            | Internal to MPC
-----------------|----------------------------|------------------
MEMC_MCK         | DDR2 Clock                 | VCO/2 (CSB*2) = 266.67Mhz
                 |                            | External to MPC
-----------------|----------------------------|------------------
USB_CLK_IN       | USB clock In               | 48Mhz
                 |                            | External to MPC, from
                 |                            | oscillator
-----------------|----------------------------|------------------
TSEC0_GTX_CLK125 | TriSpeed Ethernet0 clock   | 125Mhz
                 |                            | External to MPC, from
                 |                            | PHY PLL 25Mhz oscillator
==========================================================
DSP Clock Signal | Description                | Source
============================================================
DSP_CLKIN        | Main Clock Input           | 33.33Mhz
-----------------|----------------------------|------------------
SYSCLK1          | DSP Core Clock             | DSP_CLKIN * 9 = 300Mhz
                 |                            | Internal to DSP
-----------------|----------------------------|------------------
ECLKIN           | DSP EMIF Bus Clock         | 66.67Mhz
                 |                            | External to DSP, from
                 |                            | MPC's LCLK1
-----------------|----------------------------|------------------


Main Clock In/PCI CLK:	33.33Mhz
The 33.33Mhz clock is sourced from an onboard oscillator when in host mode.

VCO:			PCI*16 = 533Mhz
CSB:			VCO/4 (SPMF=4) = 133Mhz
eLBC or LCLK[1:0]:	CSB/2 = 66Mhz
e300 Core Clock:	CSB*2.5 = 333Mhz
DDR2 Clock:		CSB*2 = 266Mhz
USB clock In:		48Mhz
TSEC0 clock In:		25Mhz

Note:
1) For more details on MPC clocking, please refer to the MPC8313ERM, chapter 4.4.
2) For more details on DSP clocking, please refer to the PLL & PLL Controller section of the C6713B document (SPRS249B).
-------------------------------------------------
I2C Mapping
-------------------------------------------------

=================================
I2C Bus | Resource      | Address
Number  |               |
=================================
1       | BootSQCR I2C  | 0x50
        | 24LC256       |
        |---------------|---------
        | MPC-DDR2 SPD  | 0x51
        |---------------|---------
        | RTC DS1339U   | 0x68
        | (optional)    |
----------------------------------
2       | DSP-SDRAM SPD | 0x50
----------------------------------

I2C1
BootSQCR: 0x50
MPC-DDR2 SPD: 0x51
RTC DS1339U (optional): 0x68

I2C2
DSP-SDRAM SPD: 0x50

Note: For more details, please refer to the MPC8313ERM, chapter 17.

-------------------------------------------------
MPC LBC Configuration & Mapping
-------------------------------------------------

The MPC's Enhanced Local Bus Controller is configured to operate in 16 bit muxed, running at 66.67Mhz, and interfaces directly to the onboard Flash as well as the FPGA.  The FPGA acts as a bridge between the MPC eLBC and the DSP's EMIF and HPI busses.  The effective 32 bit transfer rate between the MPC's eLBC and the DSP's EMIF bus during DMA transfers peaks at 33.33MDwords/sec.

LCS0:
Configured as FCM, to interface with the NAND Flash. When the MPC is in Agent Mode, entire range is mapped on the host PCI bus occupying all of BADDR2.  The physical NAND flash size ranges from a minimum of 32Mx8 up to maximum of 4Gx8.

BMS bit = 1:
	MPC-LBC Base Addr (Bytes): 0xFF80,0000.  Default at power up in both Agent and Host modes.  However, in Host mode, Uboot will move the FCM based address to 0xE280,0000.
BMS bit = 0:
	MPC-LBC Base Addr (Bytes): 0x0.

Note: The BMS bit (Boot Memory Space) is set to '1' by the RCW inside the I2C for a default FCM address of 0xFF80,0000, which limits the FCM addressable range to 8MBytes.  In host mode, U-boot initially preserves the BMS bit value at '1', but proceeds to remap the FCM base address to 0xE280,0000, which effectively increases the addressable range to 472MBytes.

LCS1:
Configured as UPMa, to interface to the FPGA and DSP. When the MPC is in Agent Mode, entire range is mapped on the host PCI bus occupying part of BADDR1.  The UPMa base address is set to 0xFF10,0000 for Little Endian access by default, which is convenient for FPGA and DSP accesses since the DSP operates in little endian mode.  To support big endian accesses, the UPMa base address may be relocated to 0xFF00,0000.

LCS[2:3]:
Not Used.

==================================================================================
LCSn | Configuration | Resources Accessed | Physical Mapping             | Range |
==================================================================================
0    | FCM           | NAND Flash         | 0xFF80,0000 - 0xFFFF,FFFF    | 8MB   |
     |               |                    | BMS bit = 1 at power up      |       |
     |               |                    |------------------------------|-------
     |               |                    | 0xE280,0000 - 0xFFFF,FFFF    | 472MB |
     |               |                    | In Host Mode, moved by Uboot |       |
---------------------------------------------------------------------------------
1    | UPMa          | FPGA & DSP         | Little Endian (default) =    | 1MB   |
     |               |                    | 0xFF10,0000 - 0xFF1F,FFFF    |       |
     |               |                    |------------------------------|       |
     |               |                    | Big Endian =                 |       |
     |               |                    | 0xFF00,0000 - 0xFF0F,FFFF    |       |
---------------------------------------------------------------------------------
2:3  | n/a           | n/a                |                              |       |
----------------------------------------------------------------------------------

Note: For more details, please refer to the MPC8313ERM, chapters 4, 5, and 10.

-------------------------------------------------
IPIC Configuration
-------------------------------------------------
======================================
IRQn | Source  | Functionality
======================================
0    | DSP     | DSP sends an Interrupt to alert
     |         | the MPC of a pending message.
-----------------------------------------
1    | PCI Bus | Host mode INTAin from 3rd party PCI card.
     |         | Agent mode not used.
-----------------------------------------
2    | FPGA    | Open for customization
-----------------------------------------
3    | PHY     | TSEC0 Interrupt from Marvell PHY 88E1118
-----------------------------------------
4    | RTC     | Optional Real Time Clock
-----------------------------------------

IRQn0: DSP->MPC interrupt; tied to FPGA.
IRQn1: Host mode INTAin; tied to FPGA.
IRQn2: Host mode INTA/Bin; tied to FPGA.
IRQn3: TSEC0; tied to FPGA.
IRQn4: TSEC1/RTC (optional); tied to FPGA.

Note: For more details, please refer to the MPC8313ERM, chapter 8.

-------------------------------------------------
GPIO Configuration
-------------------------------------------------

============================================================================================
GPIOn | Direction | Description & Functionality                      | MPC8313 Functionality
      | for SI    | for SI Configuration                             |
============================================================================================
0     | input     | FPGA_DONEn for parallel (non-cascaded) FPGAs.    | Reserved for SI, LA0
--------------------------------------------------------------------------------------------
1     | output    | FPGA_PROGRAMn for parallel (non-cascaded) FPGAs. | Reserved for SI, LA1
--------------------------------------------------------------------------------------------
2     | output    | FPGA_DATA for parallel (non-cascaded) FPGAs.     | Reserved for SI, LA0
--------------------------------------------------------------------------------------------
3     | n/a       | n/a                                              | LA3, floating
--------------------------------------------------------------------------------------------
4     | input     | NAND Flash page size status (0=small, 1=large)   | Reserved for SI, LA4
--------------------------------------------------------------------------------------------
5:7   | n/a       | n/a                                              | LA[5:7], floating
--------------------------------------------------------------------------------------------
8:9   | n/a       | n/a                                              | UART1
--------------------------------------------------------------------------------------------
10:11 | n/a       | n/a                                              | I2C2
--------------------------------------------------------------------------------------------
12    | n/a       | n/a                                              | IRQ4
--------------------------------------------------------------------------------------------
13:14 | n/a       | n/a                                              | LA[8:9], floating
--------------------------------------------------------------------------------------------
15    | n/a       | n/a                                              | unused TSEC2/Timer lines
--------------------------------------------------------------------------------------------
16    | output    | FPGA_CLK for all FPGAs                           | Reserved for SI (unused TSEC2/Timer lines)
--------------------------------------------------------------------------------------------
17:23 | n/a       | n/a                                              | unused TSEC2 lines
--------------------------------------------------------------------------------------------
24    | output    | FPGA_DATA for daisy chained (cascaded) FPGAs.    | Reserved for SI, (unused TSEC2 lines)
--------------------------------------------------------------------------------------------
25    | output    | FPGA_PROGRAMn for daisy chained (cascaded) FPGAs.| Reserved for SI, (unused TSEC2 lines)
--------------------------------------------------------------------------------------------
26    | n/a       | n/a                                              | unused TSEC2 lines
--------------------------------------------------------------------------------------------
27    | input     | FPGA_DONEn for daisy chained (cascaded) FPGAs.   | Reserved for SI (unused TSEC2 lines)
--------------------------------------------------------------------------------------------
28:31 | n/a       | n/a                                              | SPI for microSD
--------------------------------------------------------------------------------------------



GPIO0:		input, FPGA_DONEn for parallel (non-cascaded) FPGAs.
GPIO1:		output, FPGA_PROGRAMn for parallel (non-cascaded) FPGAs.
GPIO2:		output, FPGA_DATA for parallel (non-cascaded) FPGAs.
GPIO3:		UNused, floating.
GPIO4:		input, NAND Flash page size status (0=small, 1=large)
GPIO[5:7]:	UNused, floating.
GPIO[8:9]:	n/a, UART1
GPIO[10:11]:	n/a, I2C2
GPIO12:		n/a, IRQ4
GPIO[13:14]:	UNused, floating.
GPIO15:		UNused, TSEC2/Timer lines.
GPIO16:		output, FPGA_CLK for all FPGAs
GPIO[17:23]:	unused, TSEC2 lines
GPIO24:		output, FPGA_DATA for daisy chained (cascaded) FPGAs.
GPIO25:		output, FPGA_PROGRAMn for daisy chained (cascaded) FPGAs.
GPIO26:		unused, TSEC2 lines
GPIO27:		input, FPGA_DONEn for daisy chained (cascaded) FPGAs.
GPIO[28:31]:	n/a, SPI

Note: For more details, please refer to the MPC8313ERM, chapters 3, 5 and 8.

========================================================================================
MPC Flash Organization
----------------------------------------------------------------------------------------

NAND flash is defined for a minimum of 32Mx8, and up to maximum of 4Gx8.

==========================================================================
Software Image   | Offset    | Size    | Flash Filename
==========================================================================
U-boot           | 0x0       | 2Mx8    | u-boot-nand_phy8_lp.bin (large page image)
                 |           |         -----------------------------------
                 |           |         | u-boot-nand_phy8_sp.bin (small page image)
-------------------------------------------------------------------------
Linux Kernel     | 0x20,0000 | 6Mx8    | linux.2.6.33.usbgadget (default - USB configured for gadget operation)
                 |           |         -----------------------------------
                 |           |         | linux.2.6.33.usbhost (USB configured for host operation)
--------------------------------------------------------------------------
Device Tree Blob | 0x7E,0000 | 6kx8    | simpc8313_2.6.33_8.dtb (default - USB configured for gadget operation)
                 |           |         -----------------------------------
                 |           |         | simpc8313_2.6.33_8_usbhost.dtb (USB configured for host operation)
-------------------------------------------------------------------------
File System      | 0x80,0000 | >=24Mx8 | simpc_lp.jffs2 (large page image)
                 |           |         -----------------------------------
                 |           |         | simpc_sp.jffs2 (small page image)
-------------------------------------------------------------------------

1) Uboot
	Allocated Size on Flash: 2Mx8
	Offset: 0x0
	Flash files:
		u-boot-nand_phy8_lp.bin (large page image)
		u-boot-nand_phy8_sp.bin (small page image)

2) Linux Kernel
	Allocated Size on Flash: 6Mx8
	Offset: 0x20,0000
	Flash file:
		linux.2.6.33.usbgadget (default - USB configured for gadget operation)
                linux.2.6.33.usbhost (USB configured for host operation)

3) Device Tree Blob
	Allocated Size on Flash: 6kx8
	Offset: 0x7E,0000
	Flash file:
		simpc8313_2.6.33_8.dtb (default - USB configured for gadget operation)
		simpc8313_2.6.33_8_usbhost.dtb (USB configured for host operation)

4) File System
	Allocated Size on Flash: Remaining flash, minimum 24Mx8.
	Offset: 0x80,0000
	Flash file:
		simpc_lp.jffs2 (large page image)
		simpc_sp.jffs2 (small page image)

Note:
1) when booted from NAND flash in host mode, the I2C bootSQCR is not used. However values that reside inside of the I2C1 are used by Uboot for immediate configuration of the necessary peripherals.

2) For more details, please refer to the MPC8313ERM, chapters 3, 5 and 8.

3) For more details on the software running from the MPC flash images, please refer to the MPC8313ERDBUG (User Guide - MPC8313 Reference Design Board) and the MPC8313ERDBGS (Getting Started - MPC8313 Reference Design Board), as well as the "simpc8313_board_startup.txt".

========================================================================================
I2C1 Organization
----------------------------------------------------------------------------------------

Only the following parameters should be automatically updated by the I2C bootSQCR:
  1) Reset Module (address range 0x900-0x9ff)
  2) System Configuration (address range 0x0-0x1ff)
  3) DDR2 Memory Controller (address range 0x2000-0x2fff)
  4) eLBC (address range 0x5000-0x5fff)
  5) PCI Controller (address range 0x8500-0x85ff)
  6) PCI Configuration (address range 0x8300-0x83ff)

NOTE:
1) When the DDR2 is absent, the benign System General Purpose Register Low (SGPRL) is constantly accessed by the bootSQCR with a counter ranging from 0x0-0x10. This way, the DDR2 CSRs remain in their default state at power up and other values remain in the same place.

2) The I2C bootSQCR is only used for basic initialization when in Agent mode. When in host mode, the NAND flash initializes the system, however values that reside inside of the I2C1 are used by Uboot for immediate configuration of the necessary peripherals.

----------------------------------------------------------------------------------------
I2C Offset	MPC Offset	Register		Definition
----------------------------------------------------------------------
0x00		NA		NA			0xaa55aa   (Preamble)	Ordering of bytes is right to left: 0x2_0x1_0x0
0x03		0x900		RCWLR			0x62040000
0x0a		0x904		RCWHR			0x0e146c00 (BE bit9: 0=small, 1=large)
--
0x11		0x128		DDRCDR
0x18		0x2110		DDR_SDRAM_CFG
0x1f		0xa0		DDRLAWBAR0		0x00000000
0x26		0xa4		DDRLAWAR0
0x2d		0x2000		CS0_BNDS
0x34		0x2080		CS0_CONFIG
0x3b		0x2008		CS1_BNDS
0x42		0x2084		CS1_CONFIG
0x49		0x2104		TIMING_CFG0
0x50		0x2100		TIMING_CFG3
0x57		0x2108		TIMING_CFG1
0x5e		0x210c		TIMING_CFG2
0x65		0x2118		DDR_SDRAM_MODE
0x6c		0x211c		DDR_SDRAM_MODE_2
0x73		0x2124		DDR_SDRAM_INTERVAL
0x7a		0x2114		DDR_SDRAM_CFG2
0x81		0x2130		DDR_SDRAM_CLK_CNTL
--
0x88		0x50d4		LCRR
0x8f		0x8578		PIWAR0
0x96		0x8560		PIWAR1
0x9d		0x8300		PCI_CONFIG_ADDRESS	0x2c000080 (Sub VID/DID offset)
0xa4		0x8304		PCI_CONFIG_DATA		0xbb80xx20 (Sub VID/DID)
0xab		0x8300		PCI_CONFIG_ADDRESS	0x44000080 (PCI Function Configuration Register offset)
0xb2		0x8304		PCI_CONFIG_DATA		0x01000080 (Clear CFG_LOCK)
0xb9		N/A		N/A			0x000000   (Stop)
0xbc		N/A		N/A			0xXXXXXXXX (CRC-32)

Note:
1) I2C values that reside within the offset range of 0x11-0x81 are altered with DDR2 as does the last 4 bytes of the CRC, while the others remain the same.
2) For more details, please refer to the MPC8313ERM, chapters 4 and 17.

----------------------------------------------------------------------------------------
I2C1 Image with DDR2 Absent
----------------------------------------------------------------------------------------
0x00 aa 55 aa 
0x03 7c 02 40:  64 04 00 00 
0x0A 7c 02 41:  0e 14 6c 00 
0x11 7c 00 40:  00 00 00 00 
0x18 7c 00 40:  00 00 00 01 
0x1F 7c 00 40:  00 00 00 02 
0x26 7c 00 40:  00 00 00 03 
0x2d 7c 00 40:  00 00 00 04 
0x34 7c 00 40:  00 00 00 05 
0x3B 7C 00 40:  00 00 00 06
0x42 7c 00 40:  00 00 00 07 
0x49 7c 00 40:  00 00 00 08
0x50 7c 00 40:  00 00 00 09 
0x57 7c 00 40:  00 00 00 0a 
0x5E 7c 00 40:  00 00 00 0b 
0x65 7c 00 40:  00 00 00 0c 
0x6C 7c 00 40:  00 00 00 0d
0x73 7c 00 40:  00 00 00 0e 
0x7A 7c 00 40:  00 00 00 0f
0x81 7c 00 40:  00 00 00 10 
0x88 7c 14 35:  00 00 00 02 
0x8F 7c 21 5e:  80 05 50 13 
0x96 7c 21 58:  80 05 50 16 
0x9D 7c 20 c0:  2c 00 00 80
0xA4 7c 20 c1:  bb 80 xx 20 
0xAB 7c 20 c0:  44 00 00 80
0xB2 7c 20 c1:  01 00 00 80 
0xB9 00 00 00 
0xBC 06 13 1b 7d
0xC0 ff ff ff ff ff ff ff 

----------------------------------------------------------------------------------------
I2C1 Image with DDR2 Present
----------------------------------------------------------------------------------------
0x0000 aa 55 aa 
00x003 7c 02 40:  64 04 00 00 
0x000A 7c 02 41:  0e 14 6c 00
0x0011 7c 00 4a:  73 00 00 02
0x0018 7c 08 44:  43 08 00 00
0x001F 7c 00 28:  00 00 00 00
0x0026 7c 00 29:  80 00 00 1b
0x002D 7c 08 00:  00 00 00 07
0x0034 7c 08 20:  80 84 01 02
0x003B 7c 08 02:  00 08 00 0f
0x0042 7c 08 21:  80 84 01 02
0x0049 7c 08 41:  00 22 08 02
0x0050 7c 08 40:  00 00 00 00
0x0057 7c 08 42:  37 39 73 22
0x005E 7c 08 43:  03 a0 48 c6
0x0065 7c 08 46:  44 40 02 52
0x006C 7c 08 47:  80 00 c0 00
0x0073 7c 08 49:  04 5b 01 00
0x007A 7c 08 45:  00 40 10 00
0x0081 7c 08 4c:  03 00 00 00 
0x0088 7c 14 35:  00 00 00 02
0x008F 7c 21 5e:  80 05 50 13
0x0096 7c 21 58:  80 05 50 16
0x009D 7c 20 c0:  2c 00 00 80
0x00A4 7c 20 c1:  bb 80 xx 20
0x00AB 7c 20 c0:  44 00 00 80
0x00B2 7c 20 c1:  01 00 00 80
0x00B9 00 00 00 
0x00BC e1 10 66 dd
0x00C0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

Note: The first three bytes of each field represent the boot sequencer address.

========================================================================================
FPGA Organization and Mapping.
----------------------------------------------------------------------------------------
BADDR1: FPGA Resources
=============================================================================================================
| Range   | Resource                    | MPC Base Address     | DSP CEn          | DSP Base Address        |
| (Bytes) |                             | (Byte Boundary)      | (External Space) | (Byte Boundary)         |
|         |                             | (Host or Agent Mode) |                  |                         |
=============================================================================================================
| 1M      | FPGA: 2x 32 Deep FIFOs      | 0x0-0x7,FFFF         | 0                | 0x8020,0000-0x802F,FFFF |
|         |                             | (512Kx8 Range)       |                  | (1Mx8 Range)            |
|         |-----------------------------|----------------------|                  |-------------------------|
|         | FPGA: x32 Comm Regs         | x8,0000-0x8,03FF     |                  | 0x8030,0000-0x8033,FFFF |
|         |                             | (1Kx8 Range)         |                  | (256kx8 Range)          |
|         |-----------------------------|----------------------|                  |-------------------------|
|         | FPGA: 8 of 10 CSRs          | 0x8,0400-0x8,07FF    |                  | 0x803C,0000-0x803F,FFFF |
|         |                             | (1Kx8 Range)         |                  | (256kx8 Range)          |
|         |----------------------------------------------------|------------------|-------------------------|
|         | DSP HPI Port                | 0x8,0800-0x8,0BFF    | n/a              | n/a                     |
|         |                             | (1Kx8 Range)         |                  |                         |
|         |----------------------------------------------------|------------------|-------------------------|
|         | n/a                         | 0x8,0C00-0xB,FFFF    | n/a              | n/a                     |
|         | (Not decoded)               | (253Kx8 Range)       |                  |                         |
|         |-----------------------------|----------------------|------------------|-------------------------|
|         | Expansion Module            | 0xC,0000-0xF,FFFF    | 0                | 0x8038,0000-0x803B,FFFF |
|         | (64Kx32)                    | (256Kx8 Range)       |                  | (256kx8 Range)          |
=============================================================================================================

NOTE:
1) Addresses are defined as offsets added to base addresses.
2) The PCI/LBC offsets for FPGA accesses are mirrored in two regions of 1MB, for a total of 2MB.  Accesses from the first region leave data intact for Big Endian formats, while accesses from the second region perform a byte swap for Little Endian formats, and also requires an additional value of 0x10,0000 to be added to the base address. For example, accesses to the Comm Regs can be as follows:
	2a) PCI/LBC Offset (Bytes) BE access to CommReg : [Base Address]+[0x8,0000-0x8,03FF]
	2b) PCI/LBC Offset (Bytes) LE access to CommReg : [Base Address]+[0x8,0000-0x8,03FF]+[0x10,0000]


FIFO (FPGA)
	PCI/LBC Offset (Bytes)		: 0x0-0x7,FFFF (512Kx8 Range)
	DSP-CE0 Addr (Bytes)		: 0x8020,0000-0x802F,FFFF (1Mx8 Range)
	Physical Size (Bytes/DWORDS)	: 128x8/32x32

Comm Regs (FPGA)
	PCI/LBC Offset (Bytes)		: 0x8,0000-0x8,03FF (1Kx8 Range)
	DSP-CE0 Addr (Bytes)		: 0x8030,0000-0x8033,FFFF (256kx8 Range)
	Physical Size (Bytes/DWORDS)	: 128x8/32x32
		+0: Comm Mode
		+1: Count in DWORDS
		+2: DSP Source Address
		+3: DSP Destination Address
		+4: Comm/Status Flag. Host must write 0 here before starting.
		+5: Data word (for transfer to host)
		+6: Heart beat for DMA, host comm, etc.
		+7: Main heart beat.
		+8: Host->DSP Flag/Status, HostInt->DSP
		+9: Host->DSP Message; user defined
		+10: DSP->Host Flag/Status, DSPInt->host via MPC IRQ0
		+11: DSP->Host Message; user defined
		+12-31: user defined

CSR[0:9] (FPGA)
	PCI/LBC Offset (Bytes)		: 0x8,0400-0x8,07FF (1Kx8 Range)
	DSP-CE0 Addr (Bytes)		: 0x803C,0000-0x803F,FFFF (256Kx8 range)
	Physical Size (Bytes/DWORDS)	: 64x8/16x32
		CSR0: General Control register (GRL_CTL).
		CSR1: Host Generating Interrupt Routing Mask register (HGINT_RM).
		CSR2: PCI Timeout register (PCI_TO).
		CSR3: FPGA Revision/Date register (REV_DATE).
		CSR4: DSP DMA Frame Burst Transfer Count register (DMA_FBTC).
		CSR5: DAM SDRAMAddr, referenced to DSP Addr register (DAM_SDAD).
		CSR6: DAM SDRAMCount in DWords register (DAM_SDCNT).
		CSR7: Interrupt Control register (INT_CTL).
		CSR8: DSP SDRAM Control register (DAM_CTL).
		CSR9: DSP SDRAM Extension register (DAM_EXT).
		CSR[16:10]: Unused CSRs, open for future use.



HPI (FPGA)
	PCI/LBC Offset (Bytes)		: 0x8,0800-0x8,0BFF (1Kx8 Range)
	DSP-CE0 Addr (Bytes)		: n/a
	Physical Size (Bytes/DWORDS)	: 16x8/4x32
		+0: HPIC (HPI port control register)
		+1: HPIA (HPI port address register)
		+2: HPID in Fixed Address Mode (HPI port data register in Fixed Address Mode)
		+3: HPID in Autoincrement Mode (HPI port data register in Autoincrement Mode)

Daughter/Expansion Module
	PCI/LBC Offset (Bytes)		: 0xC,0000-0xF,FFFF (256Kx8 Range)
	DSP-CE0 Addr (Bytes)		: 0x8038,0000-0x803B,FFFF (256kx8 Range)
	Physical Size (Bytes/DWORDS)	: 256Kx/64Kx32
	NOTE:	First/bottom half supports hardware wait states through the XRDYn line, second/upper half does NOT.
		XRDYn support address range: 0xC,0000-0xD,FFFF/0x8038,0000-0x8039,FFFF
		NO XRDYn support address range: 0xE,0000-0xF,FFFF/0x803A,0000-0x803B,FFFF

-------------------------------------------------
FPGA bit Loading.
-------------------------------------------------

There are two methods for FPGA bit loading:
1) Non-Cascade mode (default).
Carrier and expansion IO FPGAs are loaded separately, only sharing the clock line using the following MPC GPIOs:
FPGA_PROGRAMn:	GPIO1/LA1
FPGA_CLK:	GPIO16
FPGA_DATA:	GPIO2/LA2
FPGA_DONEn:	GPIO0/LA0

2) Cascade mode.
Carrier and expansion IO FPGAs are daisy chained using the following MPC GPIOs:
FPGA_PROGRAMn:	GPIO25
FPGA_CLK:	GPIO16
FPGA_DATA:	GPIO24
FPGA_DONEn:	GPIO27


========================================================================================
DSP Configuration
----------------------------------------------------------------------------------------
-------------------------------------------------
DSP Clocks
-------------------------------------------------

DSP Core Clock:
CLKIN = 33.33Mhzx9 = 300Mhz.
The 33Mhz clock is source from an onboard PLL circuit.

DSP EMIF Clock:
ECLKIN = 66.67Mhz.
ECKIN is sourced from the MPC8313's LBC clock.

DSP Expansion Bus Clock:
XCLK = 33.33Mhz

-------------------------------------------------
Mapping as seen from the DSP
-------------------------------------------------

CE0:
	DSP Addr (Bytes)		: 0x8000,0000-0x8FFF,FFFF
	Physical Size (Bytes/DWORDS)	: 128Mx8/32Mx32
	NOTE: The CE0 page of the EMIF bus must configured as follows:
 		Asynchronous memory
		Setup 	= 1 (or 0 if it works)
		Strobe	= 3
		Hold	= 0

CE1:
	DSP Addr (Bytes)		: 0x9000,0000-0x9FFF,FFFF
	Physical Size (Bytes/DWORDS)	: 128Mx8/32Mx32
	NOTE: Note Use.

CE2:
	DSP Addr (Bytes)		: 0xA000,0000-0xAFFF,FFFF
	Physical Size (Bytes/DWORDS)	: 128Mx8/32Mx32
	NOTE: The CE2 page of the EMIF bus must configured as follows:
		SDRAM Bank 0

CE3:
	DSP Addr (Bytes)		: 0xB000,0000-0xBFFF,FFFF
	Physical Size (Bytes/DWORDS)	: 128Mx8/32Mx32
	NOTE: The CE3 page of the EMIF bus must configured as follows:
		SDRAM Bank 1, optional.

-------------------------------------------------
DSP-CE0 Detailed Mapping
-------------------------------------------------

FIFO (FPGA)
	DSP-CE0 Addr (Bytes)		: 0x8020,0000-0x802F,FFFF (1Mx8 Range)
	Physical Size (Bytes/DWORDS)	: 128x8/32x32

Comm Regs (FPGA)
	DSP-CE0 Addr (Bytes)		: 0x8030,0000-0x8033,FFFF (256kx8 Range)
	Physical Size (Bytes/DWORDS)	: 128x8/32x32

Daughter/Expansion Module
	DSP-CE0 Addr (Bytes)		: 0x8038,0000-0x803B,FFFF (256kx8 Range)
	Physical Size (Bytes/DWORDS)	: 256Kx8/64Kx32

CSR[0:9] (FPGA)
	DSP-CE0 Addr (Bytes)		: 0x803C0000-0x803FFFFF (256Kx8 range)
	Physical Size (Bytes/DWORDS)	: 64x8/16x32

========================================================================================
CSR Details
----------------------------------------------------------------------------------------
-------------------------------------------------
CSR0: General Control register (GRL_CTL).
-------------------------------------------------


CSR0 Bits:
	0	DSP Reset
		0 = DSP in RESET - disabled.
		1 = DSP acitve - enabled.

	1..3	Reserved. Were SDRAM I2C SPD control bits, now accessed from MPC I2C2 bus.

	4	DSP-write-to-FIFO interrupt generation enable (DMAINT0)
		0 = Do not generate DSP interrupts
		1 = Automatically generate DSP ints for synchronous DMA.
	5	DSP-read-from-FIFO interrupt generation enable (DMAINT1)
		0 = Do not generate DSP interrupts
		1 = Automatically generate DSP ints for synchronous DMA.

	6..7	Reserved.

	8..9	Reserved.  Were BootMEM control bits, now HPI port is used.
	10..14: Reserved.
	15	XCLK0 clock source switch.
	16..23: Reserved.

	25..24	FIFO status, DSP to MPC half:quarter, read only
		00 = FIFO is between empty (can be empty or full) and 1/4 full.
		01 = FIFO is between 1/4 full and 1/2 full.
		10 = FIFO is between 1/2 full and 3/4 full.
		11 = FIFO is between 3/4 full and full (is not full).
	26	FIFO status, DSP to MPC empty, read only
		0 = FIFO is not empty
		1 = FIFO is empty
	27	FIFO status, DSP to MPC full, read only
		0 = FIFO is not full
		1 = FIFO is full
	29..28	FIFO status, MPC to DSP half:quarter, read only
		00 = FIFO is between empty (can be empty or full) and 1/4 full.
		01 = FIFO is between 1/4 full and 1/2 full.
		10 = FIFO is between 1/2 full and 3/4 full.
		11 = FIFO is between 3/4 full and full (is not full).
	30	FIFO status, MPC to DSP empty, read only
		0 = FIFO is not empty
		1 = FIFO is empty
	31	FIFO status, MPC to DSP full, read only
		0 = FIFO is not full
		1 = FIFO is full

-------------------------------------------------
CSR1: Host Generating Interrupt Routing Mask register (HGINT_RM).
-------------------------------------------------

CSR1 Bits:
	0	DSP_EXTINT4 <= HostInt(0) enable (see Interrupt section below)
	1	DSP_EXTINT4 <= HostInt(1) enable (see Interrupt section below)
	2	DSP_EXTINT4 <= HostInt(2) enable (see Interrupt section below)
	3	DSP_EXTINT4 <= HostInt(3) enable (see Interrupt section below)
	4	DSP_EXTINT4 <= DaughterInt(1) enable 
	5	DSP_EXTINT4 <= DaughterInt(0) enable*
	6	DSP_EXTINT4 <= DSP DMA FIFO Access interrupt enable
	7	DSP_EXTINT4 <= General Purpose

	8	DSP_EXTINT5 <= HostInt(0) enable (see Interrupt section below)
	9	DSP_EXTINT5 <= HostInt(1) enable (see Interrupt section below)*
	10	DSP_EXTINT5 <= HostInt(2) enable (see Interrupt section below)
	11	DSP_EXTINT5 <= HostInt(3) enable (see Interrupt section below)
	12	DSP_EXTINT5 <= ExpansionInt(1) enable
	13	DSP_EXTINT5 <= ExpansionInt(0) enable
	14	DSP_EXTINT5 <= DSP DMA FIFO Access interrupt enable
	15	DSP_EXTINT5 <= General Purpose

	16	DSP_EXTINT6 <= HostInt(0) enable (see Interrupt section below)
	17	DSP_EXTINT6 <= HostInt(1) enable (see Interrupt section below)
	18	DSP_EXTINT6 <= HostInt(2) enable (see Interrupt section below)
	19	DSP_EXTINT6 <= HostInt(3) enable (see Interrupt section below)
	20	DSP_EXTINT6 <= ExpansionInt(1) enable 
	21	DSP_EXTINT6 <= ExpansionInt(0) enable 
	22	DSP_EXTINT6 <= DSP DMA FIFO Access interrupt enable*
	23	DSP_EXTINT6 <= General Purpose

	24	DSP_EXTINT7 <= HostInt(0) enable (see Interrupt section below)
	25	DSP_EXTINT7 <= HostInt(1) enable (see Interrupt section below)
	26	DSP_EXTINT7 <= HostInt(2) enable (see Interrupt section below)
	27	DSP_EXTINT7 <= HostInt(3) enable (see Interrupt section below)
	28	DSP_EXTINT7 <= ExpansionInt(1) enable 
	29	DSP_EXTINT7 <= ExpansionInt(0) enable
	30	DSP_EXTINT7 <= DSP DMA FIFO Access interrupt enable
	31	DSP_EXTINT7 <= General Purpose*

NOTE:
	These signals are high asserted. When the mask bit is 1,
	corresponding interrupts are connected. If more than one bit
	is tied to one DSP interrupt, then all enabled sources are "OR"ed.
	For example,
		0x08040201: Only the host generates DSP_INT7 to DSP_INT4
		0x80400220:
			This value is defaulted.
			DSP_EXTINT7 = 	general pupose/not used.
			DSP_EXTINT6 = 	DSP DMA FIFO Access interrupt.
			DSP_EXTINT5 = 	Host generated interrupt (HostInt(1))
			DSP_EXTINT4 = 	ExpansionInt(0) interrupt.


-------------------------------------------------
CSR2: PCI Timeout register (PCI_TO).
-------------------------------------------------

CSR2 Bits:
	31..0	Timeout[31:0]

Note:  Applicable for Agent Mode only, a timeout that resets CSR regsiters if there is inactivity during a DMA transfer.

-------------------------------------------------
CSR3: FPGA Revision/Date register (REV_DATE).
-------------------------------------------------

CSR3 bits:

	31..0	0xYYMMDDRV
		0..3	V, Version, may change daily or only reflect a minor alteration to a main revision.
		4..7	R, Revision to reflect a major change.
		8..31	YYMMDD, year+month+date of compilation.

-------------------------------------------------
CSR4: DSP DMA Frame Burst Transfer Count register (DMA_FBTC).
-------------------------------------------------

CSR4 bits:
	31..16	n/a
	15..0	Xfer Count[15:0]

Descritpion: DSP's DMA burst transfer count register, which sets a limit for the number of Asynchronous DMA burst transfers to be performed by the DSP's internal EDMA engine before an external interrupt is generated by the FPGA to the DSP. The external interrupt to the DSP is used to trigger each DMA burst transfer between the DSP and the FIFO (eventually to the host), where the default value is 16 or half of the FIFO total depth.

Note:
1) To enable the interrupt from the FIFO to the DSP's DMA engine, the transfer count must be within a range between "1" and "2000".

2) In order to ensure that the MPC's Local Bus side also performs burst transfers with its own DMA engine, a multiple of 8 DWords must be entered.  Otherwise, only the DSP side will be performing burst tranfers with its DMA engine, while the MPC's Local Bus will not.

3) When the minimum value of '1' is entered, an interrupt will be generated to the DSP's DMA engine for every transfer between it and the FIFO; despite being very slow, one interrupt per DWord is very secure and minimizes the bottlenecks imposed on the EMIF bus.  On the other extreme, the maximum value entered will not cause an interrupt to the DSP until the transfer of the entire block is completed thereby rendering the maximum transfer speed between the DSP and the host; however, there is a risk that the EMIF bus can be easily bottlenecked which can cause DSP execution stalls.  As a result, the default value of '16' is the most efficient value which allows for decent data transfer speeds without excessive risk of EMIF bus bottlenecks, and hence it is strongly recommended to not be altered.

-------------------------------------------------
CSR5: DAM SDRAMAddr, referenced to DSP Addr register (DAM_SDAD).
-------------------------------------------------
Not yet implemented.

-------------------------------------------------
CSR6: DAM SDRAMCount in DWords register (DAM_SDCNT).
-------------------------------------------------
Not yet implemented.

CSR6 Bits:
	0 to 19	: DWORD Transfer Count
	20	: SDRAM Read Start
	21	: SDRAM Write Start

-------------------------------------------------
CSR7: Interrupt Control register (INT_CTL).
-------------------------------------------------
Interrupt Bits:
	0..3: 	MPC/HostInt(0:3)->DSP, MPC/Host generated interrupt to DSP.
			MPC/Host writes a high asserted value to the selected bit to trigger a LO-HI-LO pulse to the corresponding DSP Int line. Value always read as 0, since they act as pulse inputs and are not registered.  See above on CSR1, HGIRM register.
	4: 	FIFO Reset (high asserted).
		0 = FIFO in normal operation.
		1 = FIFO is reset/cleared.

	5..15: n/a

	16..20: DSP->MPC_IRQ(0:4), DSP generated interrupt to MPC/Host.
		DSP writes a high asserted value to the selected bit to generate a high asserted, level sensitive signal to the corresponding MPC/Host IRQ line. The registered value must be cleared by MPC/Host to remove interrupt.

	21 to 31: n/a

Note:
1) Host/MPC write to CSR1 with 0x0000.0010 will reset the FIFO

2) All IRQ to MPC are tristated, driven LO when asserted.

3) For DSP initiated messages, the DSP will send an interrupt to the MPC.  When the MPC is a PCI Agent (PPC is dormant), the interrupt is routed to the INTAn line on the PCI bus, thereby causing a response by the host PC.  On the other hand, when the MPC is the HOST in standalone (PPC is active), the interrupt is routed to the IPC, thereby causing a response by the PPC core.

4) For example in the case of Host/MPC->DSP interrupts,
	Assuming CSR1 is 0x08040201, we have:
		Host write to CSR7:Base+0x8,041C with 0x00000001 will cause DSP_EXTINT4
		Host write to CSR7:Base+0x8,041C with 0x00000002 will cause DSP_EXTINT5
		Host write to CSR7:Base+0x8,041C with 0x00000004 will cause DSP_EXTINT6
		Host write to CSR7:Base+0x8,041C with 0x00000008 will cause DSP_EXTINT7
		Host write to CSR7:Base+0x8,041C with 0x0000000F will cause all DSP_EXTINTs

	Assuming CSR1 is 0x04020108, we have:
		Host write to CSR7:Base+0x8,041C with 0x00000001 will cause DSP_EXTINT5
		Host write to CSR7:Base+0x8,041C with 0x00000002 will cause DSP_EXTINT6
		Host write to CSR7:Base+0x8,041C with 0x00000004 will cause DSP_EXTINT7
		Host write to CSR7:Base+0x8,041C with 0x00000008 will cause DSP_EXTINT4
		Host write to CSR7:Base+0x8,041C with 0x0000000F will cause all DSP_EXTINTs

	Assuming CSR1 is 0x04020101, we have:
		Host write to CSR7:Base+0x8,041C with 0x00000001 will cause DSP_EXTINT4 and DSP_EXTINT5
		Host write to CSR7:Base+0x8,041C with 0x00000002 will cause DSP_EXTINT6
		Host write to CSR7:Base+0x8,041C with 0x00000004 will cause DSP_EXTINT7
		Host write to CSR7:Base+0x8,041C with 0x00000008 will do nothing
		Host write to CSR7:Base+0x8,041C with 0x0000000F will cause all DSP_EXTINTs
					
	Assuming CSR1 is 0x00000000,
		No interrupts are generated to the DSP.

5) For example in the case of DSP->Host/MPC interrupts, we have:
	DSP->MPC_Irq0, DSP write to CSR7:0x803C.001C with 0x00010000 (bit 16) will cause MPC_IRQ0*
	DSP->MPC_Irq1, DSP write to CSR7:0x803C.001C with 0x00020000 (bit 17) will cause MPC_IRQ1 (shared with Host mode IntAin on the local PCI bus).
	DSP->MPC_Irq2, DSP write to CSR7:0x803C.001C with 0x00040000 (bit 18) will cause MPC_IRQ2 (shared with Host mode IntBin on the local PCI bus).
	DSP->MPC_Irq3, DSP write to CSR7:0x803C.001C with 0x00080000 (bit 19) will cause MPC_IRQ3 (shared with TSEC0 Phy).
	DSP->MPC_Irq4, DSP write to CSR7:0x803C.001C with 0x00100000 (bit 20) will cause MPC_IRQ4 (shared with optional RTC).


-------------------------------------------------
CSR8: DSP SDRAM Control register (DAM_CTL).
-------------------------------------------------

CSR8 bits:
	31      : n/a
	30      : module bank size
		0 = 2 bank SDRAM Module
		1 = 4 bank SDRAM Module

	29 to 28: SDRAM Row size, bit go out to SDRAM Bank address bits BA[1:0] defined as SDSEL[1:0]
		00 = 11 SDRAM Rows
		01 = 12 SDRAM Rows
		10 = 13 SDRAM Rows
		11 = n/a

	27 to 26: SDRAM Column size
		00 = 9 SDRAM Columns
		01 = 8 SDRAM Columns
		10 = 10 SDRAM Columns
		11 = n/a

	25      : SDRAM refresh enable
		0 = disable refresh
		1 = enable refresh

	24      : SDRAM initialization
		0 = disable initialization
		1 = enable initialization

	23 to 20: SDRAM tRCD, from SPD tRCD byte divided by 13 DSP cycles, equivalent 10nsec.
	19 to 16: SDRAM tRP, from SPD tRP byte divided by 13 DSP cycles, equivalent 10nsec.
	15 to 12: SDRAM tRC = (tRP + tRAS)/(13 DSP cycles).
	11 to 0 : n/a


Typical values:

0x6211.5000

0: n/a
1: 4 bank module
10: 13 rows
00: 9 columns
1: enable refresh
0: disable init
0001: 
0001: 
0101:

-------------------------------------------------
CSR9: DSP SDRAM Extension register (DAM_EXT).
-------------------------------------------------
Not yet implemented.

CSR9 Bits:
	31 to 0: n/a

========================================================================================
Communication Register Definitions.
----------------------------------------------------------------------------------------

	+0: CommMode[31:0]. See Communication modes section.
	+1: Count in DWORDS
	+2: DSP Source Address
	+3: DSP Destination Address
	+4: Comm/Status Flag. Host must write 0 here before starting.
	+5: Data word (for transfer to host)
	+6: Heart beat for DMA, host comm, etc.
	+7: Main heart beat.
	+8: Host->DSP Flag/Status, HostInt->DSP
	+9: Host->DSP Message; user defined
	+10: DSP->Host Flag/Status, DSPInt->host via MPC IRQ0
	+11: DSP->Host Message; user defined
	+12-31: user defined

-------------------------------------------------
FLAG Definitions:
-------------------------------------------------
	0 = Host cleared the register and ready for the DSP to run.
	1 = Valid command received from DSP and the command is being executed.
	2 = Command executed to completion correctly by DSP.
	3 = Critial error. DSP is dying or died.
	
	4 (errDSP_InvalidCommand) =
		Invalid command received.
		
	5 (errDSP_IncompleteExecution) =
		Command could not execute to completion, but was halted.

-------------------------------------------------
Comm Mode definitions:
-------------------------------------------------
1) Byte0 - Bit[7:0] = DSP/Host common modes.
2) Byte1 - Bit[15:8] = DSP mode.
3) Byte2 - Bit[23:16] = Host mode.
4) Byte3 - Bit[31:24] = N/A

1) Byte0 - Bit[7:0] DSP/Host common mode definitions:
	Bit[0]: Host (write) to DSP/Local side (read) transfer.
		0 = DSP writes, host reads.
		1 = DSP reads, host write.

	Bit[1]: DSP/Local to Host transaction complete signal.
		0 = DSP/Local alerts Host that transaction is completed by
			setting Flag.
		1 = DSP/Local alerts Host that transaction is completed by
			causing Interrupt.  At present, DSP access to PLX doorbell
			register causes a Host Interrupt. Mostly used during Add-on
			initiated access to Host.

	Bit[2]: Block / point transfer as seen by DSP
		0 = Block to block transfer.
		1 = Block to point (DSP writes, host reads)
			or point to block (DSP reads, host writes).

	Bit[3]:	DSP IO/DMA synchronization. (host generates sync method).
		0 = DSP accesses Asynchronously.
			0a = DSP IO Asynchronous:
					DSP uses programmed I/O to acess FIFO,
					with hardware synchronization/handshaking. Hardware
					synchronization takes place by asserting DSP's RDY signal
					when FIFO is inaccessible. User must be aware that SDRAM
					refresh may be vulnerable.
			0b = DSP DMA Asynchronous:
					DSP uses its DMA engine in Asynchronous mode to acess
					FIFO, with hardware synchronization/handshaking. Hardware
					synchronization takes place by asserting DSP's RDY signal
					when FIFO is inaccessible. User must be aware that SDRAM
					refresh may be vulnerable.
		1 = DSP accesses Synchronously.
			1a = DSP IO Synchronous:
					DSP uses programmed I/O to acess FIFO, with software
					synchronization/handshaking using the Flags for each
					word.  SDRAM refresh will proceed without interference.
			1b = DSP DMA Synchronous:
					DSP uses its DMA engine in Synchronous mode to access
					FIFO, with synchronizaton performed by External Interrupts
					for handshaking.  SDRAM refresh will proceed without
					interference.
	Bit[7:4]: N/A

-------------------------

2) Bit[15:8] = DSP mode definitions:

	Bit[8]: DSP transfer mode.
		0 = DSP uses programmed I/O.
		1 = DSP uses its DMA.

	Bit[15:9]: N/A

-------------------------

3) Bit[23:16] Host modes of operation definitions:
	Bit[16]: Host copy mode.
		0 = Host accesses PCI/Local Side hardware using Target/BMDMA.
		1 = Host is accessed from PCI/Local Side hardware; Local Side/Add-on
			initiated.
	Bit[17]: Host access to PCI/Local Side hardware.
		0 = Host uses Target
		1 = Host uses BMDMA
or
	Bit[17:16]: Host access mode.
		00 = Host uses Target accesses.
		01 = Host uses Block DMA accesses.
		1x = Add-on initiated; Host is accessed by PCI/LocalSide hardware.
	Bit[23:18]: N/A

========================================================================================
Software running on MPC
----------------------------------------------------------------------------------------

Note:
1) Refer to "Flash Organization" for more details on the location of the binaries and its mapping.
NAND flash is defined for a minimum of 32Mx8, and up to maximum of 4Gx8.
2) For more details on the software running from the MPC flash images, please refer to the MPC8313ERDBUG (User Guide - MPC8313 Reference Design Board) and the MPC8313ERDBGS (Getting Started - MPC8313 Reference Design Board).

Default Configuration:
MPC IP Address   = 10.196.31.84
Host IP Address  = 10.196.31.85
Host Subnet Mask = 255.255.255.0

-------------------------------------------------
Uboot
-------------------------------------------------

1) Version: 1.3.3 or later.
2) Embedded Linux Development Kit (ELDK) for PPC_6xx (the instruction set for PPC 6xx is identical to the PPC e300 core).  Distributed and maintined by Denx, and contains the cross compilers and environment. Other utility packages are also included such as VSFTPD, SELF, DROPBEAR (SSH).
3) URL - ftp://ftp.denx.de/pub/u-boot/
4) Flash details:
	Allocated Size on Flash: 2Mx8
	Offset: 0x0
	Length (for erasing): 0x200000
	Flash files:
		u-boot-nand_lp.bin (large page image)
		u-boot-nand_sp.bin (small page image)

-------------------------------------------------
Linux
-------------------------------------------------

1) Kernel: 2.6.27 or later.
2) Embedded Linux Development Kit (ELDK) for PPC_6xx (the instruction set for PPC 6xx is identical to the PPC e300 core).  Distributed and maintined by Denx, and contains the cross compilers and environment. Other utility packages are also included such as VSFTPD, SELF, DROPBEAR (SSH).
3) Not yet supported. Linux Target Image Builder (LTIB). Distributed and maintined by Freescale, a management tool using a Perl script to build binary images for Uboot, Linux, and the File System.
4) URL: http://kernel.org
5) Flash Details:
	Allocated Size on Flash: 6Mx8
	Offset: 0x20,0000
	Length (for erasing): 0x5E0000
	Flash file:
		linux.2.6.27

-------------------------------------------------
Linux Device Tree Blob
-------------------------------------------------

1) Device Tree Source file (.dts) is bundled with the Linux package, and is used to create the Device Tree Blob file (.dtb).  The .dtb file is used by Linux to extract hardware information.
2) Compiled with Device Tree Compiler (DTC), distributed and maintained by JDL.
3) URL - http://www.jdl.com/software
4) Flash Details:
	Allocated Size on Flash: 6kx8
	Offset: 0x7E,0000
	Length (for erasing): 0x20000
	Flash file:
		simpc8313_phy0.dtb (phy mapped at 0x0)
		simpc8313_phy8.dtb (phy mapped at 0x8)

-------------------------------------------------
File System
-------------------------------------------------

1) Simple Embedded Linux File System (SELF), included with the ELDK. Framework for an embedded Linux File System.
2) Flash Details:
	Allocated Size on Flash: Remaining flash, minimum 24Mx8.
	Offset: 0x80,0000
	Length (for erasing): variable with multiples of 0x100000 (per Meg).
	Flash file:
		rootfs_lp.jffs2 (large page image)
		rootfs_sp.jffs2 (small page image)

========================================================================================
MPC Flash Directory Tree
----------------------------------------------------------------------------------------

1) Script file location for autostarting SIMPC.KO driver and SISERVER.out app.
/etc/rc.d/rc.conf

Inside of the 'rc.conf' script file, add the SI script filename located inside of the /etc/rc.d/init.d/ directory.

2) SI directories

/home/si/bin/
All Linux apps such as SISAMPLE.out, SISERVER.out, SIMPC.ko, .bit,

/home/si/dsp/
All DSP COFF files.

/home/si/doc/
All documentation files.

/home/si/tmp/
All temporary files, such as log files.

/home/si/usr/
Open for all user files and apps.
========================================================================================
SI Header Definitions for Client/Server Communications.
----------------------------------------------------------------------------------------




========================================================================================
I2C BootSequencer Initialization.
----------------------------------------------------------------------------------------

1) Definitions
	a) I2C BootSQCR Write.
		  * Write preamble, RCW. Determine page size by reading GPIO4 (NOT subDID).
		  * Write DDR2 values from DDR2_I2C1.  If absent, write blanks.
		  * Write LCRR.
		  * Write PCI Regs, including subVID/DID (default 0x80BB2000).
		  * Write CRC32.
	b) Write DDR2 Section into I2C BootSQCR
		  * Write DDR2 values from DDR2_I2C1 into bootSQCR.  If absent, write blanks.
	c) Initialize Peripherals (valid I2C, no I2C writes are involved)
		* Move IMMR.
		* DDR2 enable.
		* LBC:
			* Configure and enable FCM/NAND. Determine page size by reading GPIO4 (NOT subDID).
			* Configure and enable UPM/RA.
		* FPGA Load:
			* Check FPGA_DONE bit, force the invocation of the FPGA Load menu item.

2) General steps for initialization when SISAMPLE app is loaded.
When SISAMPLE is loaded, in the the background determine subVID/DID:
	* If 0x0 (assumes HC options), invoke 'Initialize I2C BootSQCR' menu. When complete, return feedback.
	* If 0x80BB+20xx, invoke complete menu withOUT initialization (thereby allowing option to enable PPC core in Agent mode).  'Peripherals Initialization' will occur only if a variable senses that it has not been done when one of the peripherals is accessed. Once peripherals are initalized, PPC core cannot be enabled.

========================================================================================
Software Scenarios
----------------------------------------------------------------------------------------

1) Local.
PC runs "local" app (accesses PCI driver), SI-MPC-DSP operates as Agent (PPC disabled).
	SISAMPPCI->
		SISAMPLE.exe & SISAMPLIB.DLL (host PC)


2) Remote.
PC runs "client" app (accesses an Ethernet driver instead of PCI driver), and MPC operates as Host with PPC running "SISERVER" app.
	SISAMPNET->
		\SICLIENT.EXE & SICLIENTLIB.DLL (host PC)
		\SISERVER.OUT (PPC)

Note:
MPC IP Address   = 10.196.31.84
Host IP Address  = 10.196.31.85
Host Subnet Mask = 255.255.255.0

3) Virtual.
PC runs "terminal/console" app (accessed with PC console for RS-232 or Ethernet terminal), and MPC operates as Host with PPC running "local" app; same application/makefile as the "Local" SISAMPLE.EXE case, but different build.
	SISAMPNET->
		\for example, Minicom (RS-232) or SSH (ethernet) (host PC)
		\SISAMPLE.OUT (PPC), native Linux server app


-------------------------------------------------
Local Case: SISAMPLE Guidelines (MPC in Agent Mode).
-------------------------------------------------
Menu Appearance.

MPC Init Menu
 1  Initialize I2C BootSQCR
	-> 0 Write Entire I2C BootSQCR.
	-> 1 Write DDR2 Section into I2C BootSQCR
	-> 2 Write Entire I2C BootSQCR from Hexfile.
 2  Enable Core
 3  Read Configuration Space

MPC Menu (assumes I2C is valid, checks and conditionally executes Peripheral Initialization)
 4  Create Image File from Flash....
	Display suggestions.

 5  Erase NAND Flash....
	Display suggestions with addresses/ranges.

 6  Write NAND Flash....
	Display suggestions with addresses/ranges/filenames.

 7  Read I2C1 EEPROM
 8  Write I2C1 EEPROM

 9  Busmastered Read
 A  Busmastered Write (Ramp Pattern)
 B  Target Read
 C  Target Write

 D  FPGA Load

DSP Menu
 F  Coff load DSP....
	-> 0 COFF file from TI CCS....
	-> 1 QuList file from SI....
 H  DSP Active Communications....
	->0 Data Transfers....
		->0 Read
		->1 Write
			-> CommMode.....
	->1 Messaging

 0  Exit DriverDemo

----------------------------------------------------------------------------------------
Remote Case: SICLIENT & SISERVER Guidelines (MPC in Host Mode).
----------------------------------------------------------------------------------------
Note:
MPC IP Address   = 10.196.31.84
Host IP Address  = 10.196.31.85
Host Subnet Mask = 255.255.255.0
------------
Menu Appearance for SICLIENT (accesses Ethernet drivers to communicate with SISERVER).


MPC Menu
 3  Read MPC Configuration (PCI, USB, Ethernet, etc.)

Note: Screen will display following response:

PCI Configuration Space:
80 bb 20 10

Ethernet Configuration Space:
USB Configuration Space:



DSP Menu

 D  FPGA Load
	-> 0 bit file on mapped drive (using RAMdisk folder \tmp)....
	-> 1 bit file on MPC file system....

 F  Coff load DSP....
	-> 0 COFF file from TI CCS....
	-> 1 QuList file from SI....
		-> 0 COFF file on mapped drive....
		-> 1 COFF file on MPC file system....

 H  DSP Active Communications....
	->0 Data Transfers....
		->0 Read
		->1 Write
			-> CommMode.....
	->1 Messaging

 X  Stop SISERVER.out app and Exit Demo
 0  Exit Demo
========================================================================================
MPC_FPGALoad Guidelines
----------------------------------------------------------------------------------------
MPC_FPGALoad is a subsection of the SISAMPLE.EXE utility in Local/Remote cases. For the case when FPGA loading is part the SISAMPLE/SICLIENT apps, the same switches apply.

Command Prompt switches:

MPC_FPGALoad <PCI slot number> <GPIOID> <ExpansionID> <Carrier FPGA filename.extension> <optional: expansion FPGA filename>

PCI slot number: Details the PCI PnP virtual slot number.
Values=0-n

GPIOID: Details configuration of MPC GPIO lines for loading FPGAs.
0= Parallel, both FPGAs have their own lines, only sharing clock line.
1= Daisy chain, both FPGAs share the same lines.

ExpansionID: Expansion IO card ID
0= No Expansion present
68= SI-MOD68xx card is present.
66= SI-MOD66xx card is present.

Carrier FPGA filename.extension: filename of SI-MPC-DSP carrier card, supporting either the XC3S500E/1200E/1600E, and is determined by reading the SPI VID/DID fields immediately after the application is invoked.  The extension indicates the type of FPGA file to be parsed and then loaded.
*.bit= BITfile type.
*.hex= HEXfile type.

Optional Expansion FPGA filename.extension: filename of SI-MPC-DSP expansion card, supporting the FPGA type specified by the <ExpansionID> field.  The extension indicates the type of FPGA file to be prsed and then loaded.
*.bit= BITfile type.
*.hex= HEXfile type.

Example: MPC_FPGALoad 0 0 66 mpc_top.bit mod66xx.bit

========================================================================================
Error Handling in Remote Case
----------------------------------------------------------------------------------------

Truth table for general connection error scenarios:

0= False, no errors.
1= True, errors.

SICLIENT  SISERVER  Cable        Action
                    Connection
                    Router
----------------------------------------
0         0         0            Case0: 0
0         0         1            Case1: Case 2+4 should cover.
0         1         0            Case2: Client Pings every 8sec (Tping);
                                 no response close connection and goes to an 'Idle' state.
0         1         1            Case3: Same as Case 2.
1         0         0            Case4: Server in 'Operation' state sets up a 20 sec timer
                                 (2.5x Tping) that clears every time it senses activity (ping
                                 included), every 20sec (2xTping), no response then timer
                                 will trigger a jump to initial 'Listen' state.
1         0         1            Case5: Same as Case 4.
1         1         0            Case6: Same as Case 2+4.
1         1         1            Case7: Same as Case 2+4.

Note:
1) The client detects a non functional connection in the following ways:
  1a) When SIServer closes the connection or MPC Linux closes the connection (in the case something crashes), and as part of the standard close socket API, a message will be broadcast indicating that the socket is closed. Therefore, the Client, as part of its standard socket API, when performing a ping or transfer will imediately detect that the SIServer has closed the connection and because an error will be returned.
  1b) When the cable or MPC Linux crashes as in the case of a hard reset, the Client has a 2.5xTping timeout period where it waits for an SIServer response of any kind.




========================================================================================
